Data synchronization devices are generally known in the art and are used for re-synchronizing a digital signal, e.g. electrical or optical data transmitted on a high speed link, with an output or local clock signal. Existing data synchronization devices use a number of sampling algorithms which essentially differ from one another in their capability to overcome the different timing problems caused by phase jitter, phase wander and possible frequency offset between the input and output clock signals. In many existing sampling algorithms two different general principles can be recognized: the device either samples the received digital data input signal on a multiple tap delay line and organizes a switch-over between data taps based on a correlation operation performed over all the taps, or supplies the received input clock signal through a multiple tap delay line and organizes a switch-over between clock taps based on the position of the sampling edge of the clock signal in the delay line. The many variants in the implementation of these two principles differ from one another in the way they solve the switch-over problem between data taps or clock taps and in the manner they perform the correlation operation or evaluate the position of the sampling edge of the clock signal in the delay line respectively. Both these two principles have advantages and drawbacks. For instance, in the case of data sampling the delay line must be relatively long to cover possibly long successions of identical logical levels, e.g. zeroes or ones of a binary digital input signal, whereas in the case of clock signal sampling frequency errors may be corrected but at the cost of the creation of a clock signal jitter. Anyway, in the known data synchronization devices every digit of either the received data or the received clock signal has to be sampled individually. As a consequence, a relatively large amount of hardware is needed and, since the sampling frequency is generally much higher than that of the input clock signal, one has to pay attention not to loose any digit during the above tap switch-over.